1. Field of Invention
The teachings presented herein relate to electronic circuitry. More specifically, the teachings relate to methods and systems for clocking in an electronic circuit and electronic circuits incorporating the same.
2. Discussion of Related Art
With the continuous advancement of the semiconductor industry, more and more transistors can be incorporated on a single chip. This translates into the fact that a greater number of functional circuits can be realized on a single chip. As a result, not only has the real estate on an IC chip become increasingly valuable, but also the number of pins that connect the internal circuits on a single chip to the outside world need to be utilized wisely.
A timing signal such as a clock used to drive a circuit on an integrated circuit (IC) is usually supplied via one or more pins. For example, a digital clock signal, or a single-ended digital clock, may be delivered to an IC via a single pin to provide timing information. In another example, a differential analog clock may also be provided in the form of two sinusoidal waves having a certain phase shift in between. A differential analog input is widely utilized especially when the underlying circuit is operating at a high speed to reduce noise and improve precision. However, a disadvantage is its higher power consumption due to the fact that timing information needs to be extracted from the differential analog signals. For instance, timing information such as the rising and falling edges of a clock needs to be identified by, e.g., detecting the zero crossings of two sinusoidal waves.
Modern IC chips often have two pins designated for clock input. By having two pins, it enables a user to apply one of two different clock input modes. The first mode is to supply a single-ended digital input as a clock. The second mode is to supply a differential input based on which a clock can be derived. In the former case, only one pin is needed. In the later case, both pins are needed. Given this flexibility, a user may adopt a specific clock input mode based on the underlying application. Conventionally, to indicate which clock input mode is used, an additional pin is needed for signaling the clock input mode. This is shown in FIG. 1 (Prior Art).
The conventional circuit 100 in FIG. 1 supports a flexible clock input mode. The conventional circuit 100 is connected to three input pins 105, 110, and 115, among which pins 105 and 110 are designated as clock input pins (one for CLK+ and one for CLK−) and the third pin 115 is for signaling whether a single-ended mode or a differential input mode is used. Input pin 105 is for inputting a single-ended clock input which is subsequently sent to a single-ended signal buffer (SE) 125 controlled by a clock mode control circuit 120. The differential input pair (CLK+, CLK−) is provided on both pins 105 and 110 and buffered in a differential clock input buffer (DE) 130, which is also controlled by the clock mode control circuit 120.
The clock mode signal provided on pin 115 is to inform the clock mode control circuit 120 of the clock input mode currently employed. Based on such clock mode information, the clock mode control circuit 120 generates appropriate enabling signals to control either the single-ended signal buffer (SE) 125 or the differential signal buffer (DE) 130 to output a clock signal to a circuit 135.
As shown above, three pins are conventionally necessary in order to support the flexibility of selectable clock input mode. Given that pins are scare resource in modern IC chips, an improved approach is needed that can achieve the flexibility of selectable clock input mode without having to use an additional pin.